Download CMOS Integrated Switching Power Converters: A Structured by Gerard Villar Piqué PDF

By Gerard Villar Piqué

This booklet describes the established layout and optimization of effective, strength processing built-in circuits. The technique is multidisciplinary, protecting the monolithic integration of IC layout concepts, strength electronics and keep watch over idea. particularly, this publication permits readers to conceive, synthesize, layout and enforce built-in circuits with high-density high-efficiency on-chip switching energy regulators. issues coated surround the dependent layout of the on-chip strength offer, potency optimization, IC-compatible strength inductors and capacitors, energy MOSFET switches and effective swap drivers in typical CMOS applied sciences.

  • Provides a finished reference on dependent layout and optimization of absolutely monolithic strength provides for on-chip energy administration;
  • Describes a multidisciplinary process, encompassing greater built-in energy units, either energetic and reactive, in addition to complex circuit topologies and switching regulate tools, including their implementation;
  • Enables concurrent layout of compact adaptive strength provides, including system-level and circuit-level techniques.

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Extra resources for CMOS Integrated Switching Power Converters: A Structured Design Approach

Example text

Output capacitor optimized design characteristics . . . . . . . . . . Buck converter power switches optimized design characteristics . . . Compared converters main parameters . . . . . . . . . . . . . . v A and v B values along the four different converter states (large C x capacitor is considered) . . . . . . . . . . . . . . . . . . . . Switching sequence for any of the transistors of a DCM operated 3-level Buck converter (0 stands for ‘off-state’, whereas 1 stands for ‘on-state’) .

Inductor current and output ripple for a quasi-static current ramp . . Output voltage ripple and power efficiency as a function of the output capacitor and the hysteresis cycle width . . . . . . . . . . . . . Implicit switching frequency modulation resulting from hysteretic control application, for different control loop propagation delay values (system-level simulation results) . . . . . . . . . . . . . 4 Design variables and parameters classification used in the thesis .

3-level converter P2 and N2 power switches (and drivers) optimized design characteristics . . . . . . . . . . . . . . . . . . . . . 3-level converter power switches optimized design overall characteristics . . . . . . . . . . . . . . . . . . . . . . . . Channel widths of the transistors of the four power drivers (widths in microns) . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 166 167 168 174 189 191 191 191 192 193 193 242 Table of Symbols Symbol ACc ACo ACr AL AMOS Adriver Atotal B C CA CB CMIM C PAD CT C Vx C dd C gate C in C jd C mm Cn Co C out C ox C poly−poly C sd C sg Cx D1 D3 Meaning MOSCAP structure capacitive area Output capacitor occupied area MOSCAP structure routing area Inductor occupied area Power MOS occupied area Driver occupied area Total occupied area Magnetic flux density Integration capacitor in the dnN1 and dnN2 signals generation circuits (Sect.

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